1. Field of the Invention
The invention relates to the field of semiconductor microprocessors.
2. Prior Art
The present invention covers an interfacing unit forming part of a microprocessor which processor is an improved version of the Intel 80386 microprocessor, frequently referred to as the 386 processor. The 386 processor includes a 32-bit internal data bus; details of the bus for the 386 processor are described in numerous publications (Intel, 80386 and 386 are trademarks of Intel Corporation).
The 386 processor includes an on-chip memory management unit. This unit provides addressing to, for example, a cache memory, DRAMS, mass storage, etc. The processor described in this application additionally includes an on-chip cache memory as well as an on-chip floating point unit. Certain problems arise in transferring data to an on-chip cache memory and floating point unit which are better solved by the interfacing unit described in the present application. These problems involve the transfer of blocks of data such as those transferred to a cache memory or large words associated with the floating point unit.
It is not uncommon for a 16-bit or 32-bit microprocessor to be coupled to a memory or peripherals having fewer data lines. For example, a 32-bit processor may be coupled to a RAM which provides 8 bits (single bytes) of data during each memory cycle. In some cases, the processor includes a multiplexer which couples the external data lines to different "byte lanes" of the internal data bus. This, for example, allows the external memory to satisfy a processor request for a 32-bit data word with 8 bit transfers. Various signals indicating the bus size are used in prior art microprocessors. As will be seen, the present invention permits bus sizing to be done "on the fly". This capability, along with a dynamically determined "blast" (burst last) signal enhance the presently described microprocessor when compared to prior art processors.
Other prior art known to Applicant are the bus signals associated with the Multibus-including the Multibus II (Multibus is a trademark of Intel Corporation). Additionally, other prior art known to Applicant is shown in copending application, Ser. No. 006,353, filed Jan. 14, 1987 now U.S. Pat. No. 4,807,109, entitled "High Speed Local Bus and Data Transfer Method" (1024). The following prior art patents are known to Applicant: U.S. Pat. Nos. 4,570,220; 4,447,878; 4,442,484; 4,315,308; and, 4,315,310.